This invention relates to a semiconductor device, more particularly a bipolar transistor and a method of manufacturing the same.
Transistors of this type having various constructions have already been proposed. The arrangement and construction of their electrodes are more or less limited due to problems involved in the method of manufacturing. Due to these problems, miniaturization, improvement of the characteristics of such transistors and increase in the density of integrated circuits are precluded.
According to a typical method of fabricating a bipolar transistor, for example a NPN transistor, a P type base diffusion region is formed on a N type monocrystalline silicon substrate by using a well known photolithographic process and diffusion technique and then an emitter diffusion opening is formed through a silicon oxide film overlying the base diffusion region by a conventional photolithographic process. Then, a N type impurity is diffused through this opening to form an island shaped emitter region in the base region. Thereafter a base contact opening is formed by photolithographic process and an emitter electrode and a base electrode are formed in the base contact opening and the emitter diffusion opening respectively. In this manner, a conventional transistor is fabricated but this method involves the following problems.
Firstly, it is necessary to align the relative positions of four photolithographic processes of forming the base diffusion opening, the emitter diffusion opening, the base contact opening and the base and emitter electrodes in the base region. To manufacture an extremely small transistor the accuracy of these position alignment and the accuracy of these portions must be extremely high thereby decreasing the yield of satisfactory products.
If one tries to increase the yield by sacrificing the accuracy of the position alignment and the accuracy of working, the area of the base region (except the portion thereof immediately beneath the emitter region) becomes much larger than that of the emitter region thereby increasing the collector-base junction capacitance and the base resistance thereby degrading the characteristics of the transistor.
Although it has been proposed to use the base diffusion opening as a portion of the emitter region for the purpose of increasing the integrating density, the base surface concentration decreases near the outer boundary of the base region opposing the silicon oxide film thus resulting in leakage current between the collector and emitter electrodes due to the surface N type inversion caused by the contamination of the silicon oxide film. To obviate this problem it has been proposed to provide a P.sup.+ region near the outer boundary of the base region. However, when this P.sup.+ region is formed by photolithographic technique, and when a small transistor is formed, the area of the base region except for the portion thereof just beneath the emitter region increases due to the position alignment thus deteriorating the characteristics of the transistor.